1. Field of the Invention
The present invention relates to a CMOS pulse shrinking, stretching or shrink-and-stretch mixing method and device thereof. Particularly, the present invention relates to the single-stage CMOS pulse shrinking or stretching method and device thereof. More particularly, the present invention also relates to the double-stage or multi-stage CMOS pulse shrink-and-stretch mixing method and device thereof.
2. Description of the Related Art
By way of example, U.S. Pat. No. 6,288,587, entitled “CMOS Pulse Shrinking Delay Element with Deep Subnanosecond Resolution,” discloses a CMOS pulse shrinking delay element with a deep subnanosecond resolution applicable to a Time-to-Digital Converter (TDC). The CMOS pulse shrinking delay element includes at least three internal adjacent elements and can control its pulse shrinking or expanding capability by adjusting the size ratio or driving capabilities between two of the at least three internal adjacent elements.
Accordingly, the above CMOS pulse shrinking delay element can avoid adjusting an external bias voltage or can continuously calibrate the conventional CMOS pulse shrinking delay element in order to control pulse shrinking or expanding capabilities, to facilitate simplification of circuits using the delay element, to permit more precise design and control of the pulse shrinking or expanding capabilities of every element in a TDC circuit, and, in practice, to reduce single shot errors in a cyclic TDC utilizing the pulse shrinking delay element to on the order of ten picoseconds, resulting in a TDC having extremely fine resolution, excellent accuracy, low power consumption, and low sensitivity to supply voltage and ambient temperature variations.
However, there is a need of improving the conventional CMOS pulse shrinking, stretching or shrink-and-stretch mixing method and device thereof for modifying the circuit structure and enhancing the functions (e.g. resolution problem). The above-mentioned patent is incorporated herein by reference for purposes including, but not limited to, indicating the background of the present invention and illustrating the situation of the art.
As is described in greater detail below, the present invention provides a CMOS pulse shrinking, stretching or shrink-and-stretch mixing method and device thereof. A plurality of homogeneous logic elements and at least one odd-positioned inhomogeneous logic element (or even-positioned inhomogeneous logic element) is combined to form a pulse shrinking or stretching device. The odd-positioned inhomogeneous logic element (or the even-positioned inhomogeneous logic element) is applied to stretch (or shrink) pulse signals for minimizing dimensions or areas of the circuit and increasing resolution of the device in such a way to mitigate and overcome the above problem. Also, the homogeneous logic elements, at least one of the odd-positioned inhomogeneous logic elements and at least one of the even-positioned inhomogeneous logic elements are combined to form a pulse shrink-and-stretch mixing device.